Custom Memory Allocator
A C allocator with address-sorted free lists, coalescing, and in-place realloc growth, built for CS 341.
1stof 400 · CS 341 Malloc Contest
01 / Work
What I've built
24 projects
Sentinel
An assistant for homelab administration, with dry-run previews and confirmation before infrastructure changes.
Dry runreview changes before execution
GPT-2 Inference Engine in CUDA
Built with a four-person team; my work included FlashAttention-2, memory tiling, and CUDA kernel profiling.
24.2×team end-to-end speedup on A40
FPGA Scheduling Research
Host–FPGA pipeline for hardware scheduling; implementing a zero-copy ring-buffer interface.
Research source private · co-authored paper available
Stint Studio
An iOS drive logger with recorded stints, map views, and manual trip assembly.
EnvSync
Encrypted .env sharing for my ACM team, with a Rust CLI, version history, and a Next.js dashboard.
Periscope
Publishes self-hosted web services through a VPN exit and reverse proxy, keeping the home IP private.
1public service port
Vega
A local-model trading experiment with four research personas and a separate risk-control layer.
4personas with separate portfolios
VPN-Gated Media Stack
Containerized media services with outbound traffic routed through a VPN and protected by a kill-switch.
VPNoutbound traffic gated by the tunnel
Minecraft Server + CraftDeck
A Fabric server for friends with a Next.js operations panel for server management.
K3s Home Lab Cluster
Self-hosted services across two Linux hosts and a three-node HA K3s cluster, with automated deployment and monitoring.
3HA K3s nodes on Proxmox
Socratic Code Companion
A VS Code companion that uses a local model to guide code review through questions.
Freeway
A self-hosted LLM gateway with one API for 12 providers, caching, failover, and quota management.
80%fewer paid calls · 184-request benchmark
Schema — Document Search
Document search over PDFs and handwritten notes, with retrieved passages supporting model responses.
AI Journaling Platform
A journaling application that combines calendar context and webcam analysis to suggest reflection prompts.
Pathway to Improved Cities
Urban-data analysis using machine learning and spatial methods to explore disparities in Chicago services.
Nonstop Networking
A C epoll server supporting thousands of concurrent TCP clients with nonblocking per-connection state machines.
UIUC honor code — source is private
Parallel Make
A multithreaded make implementation that schedules build dependencies using a DAG, mutexes, and condition variables.
UIUC honor code — source is private
sshell — POSIX Shell
A POSIX shell in C with command parsing, redirection, signal handling, and process management.
UIUC honor code — source is private
Finding Filesystems
A filesystem reader in C that traverses directories and files directly from a raw ext2 image.
UIUC honor code — source is private
Autonomous Maze Solver
A Raspberry Pi Pico maze-solving robot built in C/C++, with sensor integration and dual-core processing.
XRayPDF
A PDF inspection tool for hidden text layers, low-contrast content, and text stored in metadata.
Seafile + mTLS
A Seafile desktop-client fork with client-certificate support for mutual TLS authentication.
Digit Net From Scratch
An MNIST classifier in Java, with neural-network training and backpropagation implemented from scratch.
02 / Experience
Experience
University of Illinois Chicago
LocationChicago, IL
TypeResearch · Prof. Debjit Pal's group
HPC scheduling across software and FPGA hardware.
- 01Coauthored BoostedSOSA, a dual-FPGA scheduler that uses ML predictions of job runtime. The team's evaluation reports up to 63.85% lower prediction error than user estimates and an average 17× speedup over an AVX-optimized software baseline.
- 02Currently implementing two zero-copy, lock-free host–FPGA ring buffers to replace flag polling and reduce PCIe handoff overhead. The integration is still in progress.
Coauthored research · BoostedSOSARead paper
University of Illinois Chicago
LocationChicago, IL
TypeInternship
From batch I/O to a continuous scheduling pipeline.
- 01Converted an FPGA scheduler from batch-oriented I/O into a free-running streaming pipeline, so jobs could be scheduled as they arrived.
- 02Built nonblocking Vitis HLS Reader/Writer kernels and multithreaded C++/XRT host I/O for continuous job dispatch.
- 03Designed and verified the systolic scheduling datapath, virtual FIFO, and cost calculator with roughly 1,100 lines of Monte Carlo-driven Vitis HLS tests on an Alveo U55C.
03 / Skills
What I work with
6 groups
01
Languages
02
Full stack & data
03
Linux & HPC
04
Hardware & FPGA
05
Infrastructure & DevOps
06
AI / ML
04 / Recognition
Recognition
4 entries
1stCS 341 Malloc Performance ContestTop-performing memory allocator among 400 students.2025
4thUIUC Capture-the-Flag — Advanced TrackFourth place in the advanced track of UIUC CTF.2026
3rdUIUC Capture-the-Flag (CTF)Third place at UIUC CTF.2025
5thScience Olympiad — Robot TourAutonomous Pi Pico maze robot; 5th of 50 schools at UIUC State Science Olympiad.2024
05 / About
About
I'm studying Computer Science and Mathematics at UIUC, graduating in 2028. I work on full stack applications, Linux infrastructure, and low level systems in C/C++, CUDA, and FPGA research. I also operate websites and projects serving 30K+ monthly unique visitors and over a million requests per month. I enjoy understanding how things work and making them reliable.
06 / Contact
Get intouch.
© 2026 · Aryan SinghBuilt and deployed from my own cluster